1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit with scan-path.
2. Description of the Related Art
Recently, semiconductor circuit's structure has become large and complex. To accomplish easy function test of these semiconductor circuits, DFT(Design-for-Testability) with scan-path has been adopted. The scan-path is a shift register chain configured by a plurality of flip-flops (FFs) inserted in logic circuit, operating synchronously with clock signal, whereby the FFs are switched to configure shift register by switching circuit on test-mode operation. The function test of a combination circuit can be done easily by applying test dada at any point in the combination circuit by utilizing the scan-path or reading out a signal on any point of the combination circuit thorough the scan-path.
FIG. 1 shows a structure of a semiconductor integrated circuit with scan-path of related art. This semiconductor integrated circuit complies an input/output (I/O) terminal 1A, 1B, and combination circuit 2 executing predetermined logical operation. A plurality of FFs with scan function (S-FF) 31,32, . . . , 3n are inserted at various positions of the combination circuit 2. Each S-FF 31, . . . , 3n has a similar construction such as shown by S-FF 31 and complies a selector 3a and a FF 3b. 
The selector 3a selects a signal of terminal A when a test mode is set by a mode signal MOD, and selects signal of terminal B when a normal operation mode is set by the MOD. The FF 3b retains and outputs a selected signal by the selector 3a according to the clock signal (not shown). An output signal from combination circuit 2 is fed to the terminal B of the selector 3a and the output signal (synchronized with clock signal) of FF 3b is fed to the combination circuit 2. The output signal of FF 3b is also fed to the terminal A of selector 3a of subsequent S-FF 32 via signal path 41.
Meanwhile, the I/O terminal 1A is connected to a terminal I of the combination circuit 2 and to the terminal A of the selector 3a of the S-FF 31 via selector 5. The selector 5 feeds the signal of the I/O terminal to the S-FF 31 when the test mode is set by the MOD and feeds the signal to the combination circuit 2 when normal operation mode is set by the MOD.
An output signal of the last stage S-FF 3n and an output signal of an output terminal O of the combination circuit are fed to the output terminal 1B via a selector 6. The selector 6 selects an output signal from S-FF 3n of terminal A when test mode is set by the MOD and selects an output signal from the combination circuit 2 of terminal B when normal operation mode is set by the MOD.
The operation of above mentioned semiconductor integrated circuit of the prior art will be described below.
Firstly, when the test mode is set by the mode signal MOD, the selector 3a of each S-FF 31-3n and the selector 5,6 are all switched to terminal A. Thus, a scan-path from the I/O terminal 1A to the I/O terminal 1B via selector 5,S-FF 31-3n is formed.
The n test-data are then sequentially applied to the I/O terminal 1A synchronously with the clock signal. A plurality of inputted test-data are herewith stored by each FF 3b in S-FF 31-3n. As the plurality of test-data stored by each of the FF 3b are also fed to the combination circuit 2, a signal corresponding to the given test-data is outputted from the combination circuit 2. The signal from the combination circuit 2 is supplied to each terminal B of each selector 3a of S-FF 31-3n.
In this state of things, the semiconductor integrated circuit is set to normal operation state by the mode signal MOD, and is given only one pulse clock signal. The signals being outputted from combination circuit according to the test-data are herewith retained in each FF 3b of S-FF 31-3n.
The mode signal MOD is switched back to the test-mode and clock signal is fed to the semiconductor integrated circuit. The signals retained in each FF 3b are outputted sequentially from I/O terminal 1B. A determination whether the signal from terminal 1B is corresponding to the test-data is made and the functions of the combination circuit 2 is tested.
In this semiconductor integrated circuit, when normal operation mode is set by the mode signal MOD, the selectors 3a in each S-FF 31-3n and the selector 5,6 are all switched to terminal B. A plurality of paths 4 connected sequentially between neighboring S-FF 3 are shut down and each S-FF 3 operates as timing adjusting FF, which retains the signal from the combination circuit 2 and outputs it synchronously with clock signals.
A test circuit that can change a length of scan-path by selecting a plurality of paths to be tested freely among a plurality of combination circuits grouped by scan-path is disclosed in Japanese Laid-open Publication No. 5-142298, and another example is disclosed in Japanese Laid-open Publication No. 2002-9238. A design method of scan-path is disclosed in latter literature, that is, in a semiconductor integrated circuit with a plurality of combination circuits with scan-path, each scan-path length is equalized for reducing test execution time.
In a conventional scan-path circuit, a pair of I/O terminal 1A,1B are needed for one scan-path. On the other hand, according to the large scaling and complexity of semiconductor integrated circuit, the number of S-FFs 3 connected to the combination circuit 2 is increasing dramatically. But to increase the number of I/O terminals is difficult depending on the number of S-FFs. Therefore the number of scan-FFs that consists of one scan-path increases, so a test time needed is increasing.